Modeling Thermal Stresses of Copper Interconnects in 3D IC Structures

Bentz, D.N., Zhang, J., Bloomfield, M., Lu, J-Q., Gutmann, R.J., Cale, T.S.
Rensselaer Polytechnic Institute

One of the key issues in developing higher density microelectronics devices is the impact of the stresses induced by thermal expansion mismatches of the materials used.

We have examined, using FEMLAB, the stresses due to interwafer copper interconnects embedded in multilayer structures created by bonding two wafers using an organic low-k dielectric glue, benzocylcobutene (BCB). This work indicates that there are reasons to be concerned about stress induced failures, in both the Cu vias and in thinned Si wafers, due to differences in coefficient of thermal expansion (CTE) values for relevant materials.

As experimental stress data on 3D ICs are not readily available, we validate our simulation approach using experimental data from two types of planar systems.

After validating our simulation approach using experimental data from planar systems, we applied it to the 3D IC system [1]. The system of particular interest is that of Cu inter-wafer vias through a seven -layer 3D IC stack terminated with a Cu pad.

Depending upon the pitch and size of the Cu vias, for a given BCB thickness Cu failure is a concern. Conversely, when Cu pitches are small and/or Cu vias are large enough, failure of the thinned Si wafer is possible. We suggest using a collar, made from a low modulus dielectric to minimize this risk.

This topic is continued in id: 1347.

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